Nanoscale thermal management - IEEE Potentials

0278-6648/02/$17.00 © 2002 IEEE 11 he transistor counts on the high-end microprocessor is rushing toward the 400-million mark and the feature dimensions are shrinking toward the nanometer scale. As a result, the thermal properties of semiconductor nanostructures are beginning to attract significant attention. Several major factors explain the recent interest to investigate thermal conductivity in quantum confined structures. The most important one is a continuous scaling down of the feature sizes in electronic devices and circuits. This leads to an increase in power dissipation per unit area despite the reduction of the power supply voltage. In addition, a variety of size effects that manifest themselves at the nanoscale are very interesting from the physics point of view. To achieve increased computer chip performance and reduce cost, for the past three decades the semiconductor industry has pursued a strategy of decreasing the feature size of devices with each new product generation or technology node. The technology node is defined by the smallest device or circuit feature size. Conventionally, this feature element is the half-pitch of the first level interconnect lines in the dynamic random access memory (DRAM) or the transistor gate length. Following the projections of the International Technology Roadmap for Semiconductors, the industry will reach the 70-nanometer technology node by the year 2008. The 70-nanometer technology node corresponds to the feature size of 70 nanometers or 7 x 10–8 meters. For comparison, the feature size of state-of-the-art devices is 0.18 micrometers. Thus, rather soon, the electronic industry will completely enter the realm of nanoscale and face many new challenges. Scaling transistors to the nanometer scale is plagued with challenges. Some examples are quantum mechanical gate tunneling, electron mobility degradation, and reliability problems due to statistical fluctuations in the positioning of dopant atoms. A specific problem is related to interconnects. Making interconnnects smaller, unlike transistors, does not enhance their performance. For example, it is predicted that the intrinsic delay-time of the 1-mm-long interconnect at the 35 nm technology node will overwhelm the transistor’s delay-time by two orders of magnitude: 250 ps vs 2.5 ps. With more interconnects and smaller transistor feature size, the thermal resistance of the integrated circuit